The cooperative relationship between data processing host systems and attached peripheral systems, including peripheral data storage systems, requires the exchange of control signals for ensuring system and data integrity. Included in such control are resetting capabilities. A host system can send a reset peripheral command to a peripheral system for reestablishing a predetermined operational state within one or more devices of the peripheral system. Such resetting is useful for error recovery purposes, as well as recalibration and the like. In general, two types of resets may occur in a peripheral system. Firstly, a so-called selective reset is performed through input/outout channels or connections. When certain peripheral device/peripheral systems malfunctions are detected, a selective reset enables the input/output channel to signal the device connected to the channel to reset to a predetermined restartable operational state. Secondly, a system reset occurs when the host system performs an internal reset, an initial program reset, system clear reset or a power on reset. The peripheral system reset causes the input/output connection to conclude operations on selected channels and subchannels connected to such host. Devices are selectively reset in accordance with the type of reset command. Status information contained in subchannels as well as interruption conditions are reset. The peripheral system responds by resetting all devices and operations relatable to the input/output channel that supplied the system reset signal. It should be appreciated that because of the diversity of peripheral systems and peripheral devices that the particular reset operation can vary widely. A common requirement is that the peripheral system and device each reset to a predetermined restartable or reference operational state. In some situations, a selective reset may effect only the peripheral device without affecting a control unit that is usually interposed between the host system and the peripheral device.
In most peripheral systems each peripheral device is addressable through a single unique address, i.e. while access may be multipath, the device is always uniquely defined in the system. Certain paging and swapping peripheral systems employ a plurality of addresses for each peripheral device. Each of the addresses for the physical device can be termed an "exposure"; also referred to as a "logical device" of the peripheral system. Each logical device will have its own unique address; preferably that unique address is easily relatable to the physical peripheral device. The peripheral system preferably employs an addressing scheme and control such that each logical device is independent of the other logical devices. This arrangement results in a plurality of diverse operational states for a single peripheral device; one unique operational state for each of the logical devices used to access the physical device. Further, a peripheral system can combine operations for the single physical device from all of the logical devices. Such combination, particularly work queues, can raise the efficiency of the peripheral system and hence reduce access time as well as cost of operations.
When resetting a logical device, such reset to a restart position should not affect the other independent logical devices. When common work queues and accesses to a single peripheral device from a plurality of logical devices occurs, the reset may be inadvertently propagated to other logical devices through the commonality of the operations. In a peripheral storage system, a cache memory may be employed in connection with a backing store having a retentive storage properties, such as a direct access storage device (DASD) which usually includes disk storage apparatus. The data in the cache is accessible through any of the logical devices. Accordingly, controls must be implemented to ensure that resetting a given logical device does not inadvertently remove or alter access to data stored in the cache that is intended for another logical device.